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Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.

C. Ding, A. Ren, G. Yuan, X. Ma, J. Li, N. Liu, B. Yuan, and Y. Wang. ACM Great Lakes Symposium on VLSI, page 353-358. ACM, (2018)

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Klaus Geng

Hui Geng

Hong Geng

Xiaoyun Geng

Geng Lai

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A Life-Cycle Energy and Inventory Analysis of Adiabatic Quantum-Flux-Parametron Circuits.M. Zabihi, Y. Xie, Z. Li, P. Dong, G. Yuan, O. Chen, M. Pedram, and Y. Wang. CoRR, (2023)Achieving Real-Time Execution of Transformer-based Large-scale Models on Mobile with Compiler-aware Neural Architecture Optimization.W. Niu, Z. Kong, G. Yuan, W. Jiang, J. Guan, C. Ding, P. Zhao, S. Liu, B. Ren, and Y. Wang. CoRR, (2020)A SOT-MRAM-based Processing-In-Memory Engine for Highly Compressed DNN Implementation.G. Yuan, X. Ma, S. Lin, Z. Li, and C. Ding. CoRR, (2019)An Efficient End-to-End Deep Learning Training Framework via Fine-Grained Pattern-Based Pruning.C. Zhang, G. Yuan, W. Niu, J. Tian, S. Jin, D. Zhuang, Z. Jiang, Y. Wang, B. Ren, S. Song and 1 other author(s). CoRR, (2020)Memristor crossbar-based ultra-efficient next-generation baseband processors.G. Yuan, C. Ding, R. Cai, X. Ma, Z. Zhao, A. Ren, B. Yuan, and Y. Wang. MWSCAS, page 1121-1124. IEEE, (2017)Towards Real-Time Segmentation on the Edge.Y. Li, C. Yang, P. Zhao, G. Yuan, W. Niu, J. Guan, H. Tang, M. Qin, Q. Jin, B. Ren and 2 other author(s). AAAI, page 1468-1476. AAAI Press, (2023)Peeling the Onion: Hierarchical Reduction of Data Redundancy for Efficient Vision Transformer Training.Z. Kong, H. Ma, G. Yuan, M. Sun, Y. Xie, P. Dong, X. Meng, X. Shen, H. Tang, M. Qin and 5 other author(s). AAAI, page 8360-8368. AAAI Press, (2023)YOLObile: Real-Time Object Detection on Mobile Devices via Compression-Compilation Co-Design.Y. Cai, H. Li, G. Yuan, W. Niu, Y. Li, X. Tang, B. Ren, and Y. Wang. AAAI, page 955-963. AAAI Press, (2021)SupeRBNN: Randomized Binary Neural Network Using Adiabatic Superconductor Josephson Devices.Z. Li, G. Yuan, T. Yamauchi, M. Zabihi, Y. Xie, P. Dong, X. Tang, N. Yoshikawa, D. Tiwari, Y. Wang and 1 other author(s). MICRO, page 584-598. ACM, (2023)ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN Training.S. Chang, G. Yuan, A. Lu, M. Sun, Y. Li, X. Ma, Z. Li, Y. Xie, M. Qin, X. Lin and 2 other author(s). DATE, page 1-6. IEEE, (2023)

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Disambiguation of "Yuan, Geng"

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Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.

Please choose a person to relate this publication to

Klaus Geng

Hui Geng

Hong Geng

Xiaoyun Geng

Geng Lai

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yuan, Geng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.

Please choose a person to relate this publication to

Klaus Geng

Hui Geng

Hong Geng

Xiaoyun Geng

Geng Lai

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.