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Low Precision RNNs: Quantizing RNNs Without Losing Accuracy., , and . CoRR, (2017)Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy., and . ICLR (Poster), OpenReview.net, (2018)WRPN: Wide Reduced-Precision Networks., , , and . CoRR, (2017)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC., , , , , , , , , and 1 other author(s). FPL, page 106-110. IEEE Computer Society, (2018)High performance binary neural networks on the Xeon+FPGA™ platform., , , , , , and . FPL, page 1-4. IEEE, (2017)Customizable FPGA OpenCL matrix multiply design template for deep neural networks., , , , , , , and . FPT, page 259-262. IEEE, (2017)Guest Editors' Introduction: Hardware Accelerators for Data Centers., , and . IEEE Des. Test, 35 (1): 5-6 (2018)Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy., and . CoRR, (2017)Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI., , , , , , , , , and 6 other author(s). FPGA, page 119. ACM, (2019)Efficient Execution of Bursty Applications., , , and . IEEE Comput. Archit. Lett., 15 (2): 85-88 (2016)