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Disambiguation of "Young, Brian"

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A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS.

, , , , , and . VLSIC, page 256-. IEEE, (2015)

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Rolf-Walter Briant

Benoît Briand

Grady Leon Young

Christopher Young

Ursula Brian

 

Other publications of authors with the same name

A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators., , , , , and . VLSIC, page 1-2. IEEE, (2014)A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques., , , and . IEEE J. Solid State Circuits, 49 (5): 1184-1197 (2014)Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops., , , and . IEEE J. Solid State Circuits, 48 (6): 1416-1428 (2013)A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links., , , , and . IEEE J. Solid State Circuits, 49 (10): 2243-2258 (2014)Effectiveness of Individual and Dyadic Training Protocols: The Influence of Trainee Interaction Anxiety., , , and . Hum. Factors, 38 (1): 79-86 (1996)Automated posteriorwall thickness measurement from B-mode ultrasound., , , , and . ISBI, page 77-80. IEEE, (2013)The NomBank Project: An Interim Report., , , , , , and . FCP@NAACL-HLT, (2004)Model and analysis for combined package and on-chip power grid simulation., , , , , and . ISLPED, page 179-184. ACM, (2000)A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 52 (9): 2306-2320 (2017)A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators., , , and . ISSCC, page 464-466. IEEE, (2012)