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Disambiguation of "Lapotre, Vianney"

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Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm.

, , , , , and . IEEE Trans. Computers, 67 (3): 335-347 (2018)

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Vianney Bizimana

Vianney Jouhet

 

Other publications of authors with the same name

PAnTHErS: A Prototyping and Analysis Tool for Homomorphic Encryption Schemes., , and . SECRYPT, page 359-366. SciTePress, (2017)A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components., , , , , , and . AsianHOST, page 92-97. IEEE, (2018)The Kingsguard OS-level mitigation against cache side-channel attacks using runtime detection., , , , and . Ann. des Télécommunications, 77 (11-12): 731-747 (2022)Contributions à la sécurité des systèmes embarqués face aux attaques logiques et physiques. (Contributions to the security of embedded systems against logical and physical attacks).. (2023)On The Effect of Replacement Policies on The Security of Randomized Cache Architectures., , , , , , and . CoRR, (2023)NIGHTs-WATCH: a cache-based side-channel intrusion detector using hardware performance counters., , , , , and . HASP@ISCA, page 1:1-1:8. ACM, (2018)WHISPER: A Tool for Run-Time Detection of Side-Channel Attacks., , , , , , and . IEEE Access, (2020)Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections., , , , , , , and . EuroS&P Workshops, page 304-310. IEEE, (2023)Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation., , , and . ISCAS, page 1-4. IEEE, (2020)A small and adaptive coprocessor for information flow tracking in ARM SoCs., , , , , , and . ReConFig, page 1-8. IEEE, (2018)