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Low-Cost Fault Localization and Error Correction for a Signed Digit Adder Design Utilizing the Self-Dual Concept.

, and . DSD, page 276-279. IEEE Computer Society, (2015)

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Constant-Factor Redundant CORDIC for Angle Calculation and Rotation., and . IEEE Trans. Computers, 41 (8): 1016-1025 (1992)Discrete Fourier transform processors using CORDIC., and . Great Lakes Symposium on VLSI, page 260-265. IEEE, (1991)A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only)., and . FPGA, page 270. ACM, (2013)Operation Net System: A Formal Design Representation Model for High-Level Synthesis of Asynchronous Systems Based on Transformations., , and . ICATPN, volume 3099 of Lecture Notes in Computer Science, page 435-453. Springer, (2004)A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip., and . Microprocess. Microsystems, 38 (5): 375-398 (2014)Bio-inspired self-aware fault-tolerant routing protocol for network-on-chip architectures using Particle Swarm Optimization., and . Microprocess. Microsystems, (2017)Low Latency and High Throughput Pipelined Online Adder for Streaming Inner Product., , , , , and . J. Signal Process. Syst., 95 (7): 815-829 (July 2023)Adder with Reduced Latency and Minimized Interconnect for Streaming Inner Products., , , and . ACSCC, page 938-942. IEEE, (2021)Design and Evaluation of a Cache Coherence Adapter for the SMP Nodes Interconnected via Xcent-Net., , , , and . ISCIS, volume 2869 of Lecture Notes in Computer Science, page 908-915. Springer, (2003)Low-cost Hardware Redundancy for Fault-mitigation in Power-constrained IoT Systems., and . ICTC, page 60-62. IEEE, (2020)