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Disambiguation of "Balachandra, Nithin Kumar Yernad"

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Process Corner Calibration for Standard Cell Based Flash ADC.

, , , and . iSES, page 195-200. IEEE, (2019)

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Other publications of authors with the same name

System level fault-tolerance core mapping and FPGA-based verification of NoC., , and . Microelectron. J., (2017)6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process., , , , and . IET Circuits Devices Syst., 14 (3): 340-346 (2020)Process Corner Calibration for Standard Cell Based Flash ADC., , , and . iSES, page 195-200. IEEE, (2019)An energy-efficient fault-aware core mapping in mesh-based network on chip systems., , and . J. Netw. Comput. Appl., (2018)Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic., , , and . IEEE Access, (2021)Design and implementation of image kernels using reversible logic gates., , , and . IET Image Process., 14 (16): 4110-4121 (2020)Hardware implementation of fault tolerance NoC core mapping., , and . Telecommun. Syst., 68 (4): 621-630 (2018)High-performance and energy-efficient fault-tolerance core mapping in NoC., , and . Sustain. Comput. Informatics Syst., (2017)Two-Step Flash ADC Using Standard Cell Based Flash ADCs., , , , and . iSES, page 292-295. IEEE, (2019)Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures., , and . Wireless Personal Communications, 100 (2): 213-225 (2018)