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Impact of process variations on computers used for image processing., , , и . ISCAS, стр. 1444-1447. IEEE, (2012)SEU tolerant SRAM cell., , , , и . ISQED, стр. 597-602. IEEE, (2011)Identifying high variability speed-limiting paths under aging., , , и . LATS, стр. 1-6. IEEE, (2017)Improving post-silicon error detection with topological selection of trace signals., , , , и . VLSI-SoC, стр. 1-6. IEEE, (2017)ATPG power guards: On limiting the test power below threshold., и . DATE, стр. 301-304. IEEE, (2018)Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors., , , и . DATE, стр. 1572-1577. IEEE Computer Society, (2010)An efficient test technique to prevent scan-based side-channel attacks., , и . ETS, стр. 1-2. IEEE, (2017)Polynomial coefficient based DC testing of non-linear analog circuits., , и . ACM Great Lakes Symposium on VLSI, стр. 69-74. ACM, (2009)A high performance scan flip-flop design for serial and mixed mode scan test., , , и . IOLTS, стр. 233-238. IEEE, (2016)ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits., , и . VDAT, том 7373 из Lecture Notes in Computer Science, стр. 172-179. Springer, (2012)