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A Time-Interleaved Multimode ΔΣ RF-DAC for Direct Digital-to-RF Synthesis.

, , , , , , , and . IEEE J. Solid State Circuits, 51 (5): 1109-1124 (2016)

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Analytical and experimental study of tuning range limitation in mm-wave CMOS LC-VCOs., , , and . ISCAS, page 2468-2471. IEEE, (2013)A 10mW 37.8GHz current-redistribution BiCMOS VCO with an average FOMT of -193.5dBc/Hz., , , , , , , , and . ISSCC, page 150-151. IEEE, (2013)A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver., , , , , and . IEEE J. Solid State Circuits, 53 (9): 2500-2511 (2018)16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDR., , , , , , , and . ISSCC, page 286-287. IEEE, (2017)Frequency Tuning Range Extension in LC-VCOs Using Negative-Capacitance Circuits., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (4): 182-186 (2013)Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (6): 2037-2050 (2019)Systematic Analysis of Interleaved Digital-to-Analog Converters., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (12): 882-886 (2011)A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR., , , , , , , , and . IEEE J. Solid State Circuits, 52 (12): 3262-3275 (2017)A Time-Interleaved Multimode ΔΣ RF-DAC for Direct Digital-to-RF Synthesis., , , , , , , and . IEEE J. Solid State Circuits, 51 (5): 1109-1124 (2016)