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Disambiguation of "Dupaix, Brian"

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A Time-Interleaved Multimode ΔΣ RF-DAC for Direct Digital-to-RF Synthesis.

, , , , , , , and . IEEE J. Solid State Circuits, 51 (5): 1109-1124 (2016)

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Rolf-Walter Briant

Benoît Briand

Ursula Brian

Annette Brians

Brian Alexander

 

Other publications of authors with the same name

Wide-Bandwidth, High-Linearity, 2.8-GS/s, 10-bit Accurate Sample and Hold Amplifier in 130-nm SiGe BiCMOS., , , , , , , , , and 1 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (5): 1758-1768 (2019)A fully-integrated switched capacitor voltage regulator for near-threshold applications., , , and . ISCAS, page 201-204. IEEE, (2015)Vulnerabilities and Reliability of ReRAM Based PUFs and Memory Logic., , , and . IEEE Trans. Reliab., 69 (2): 690-698 (2020)An on-chip resonant-gate-drive switched-capacitor converter for near-threshold computing achieving 70.2% efficiency at 0.92A/mm2 current density and 0.4V output., , , , , and . ISSCC, page 438-440. IEEE, (2018)Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (6): 2037-2050 (2019)16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDR., , , , , , , and . ISSCC, page 286-287. IEEE, (2017)A High Linearity, 2.8 GS/s, 10-bit Accurate, Sample and Hold Amplifier in 130 nm SiGe BiCMOS., , , , , , , , and . ISCAS, page 1-4. IEEE, (2018)A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver., , , , , and . IEEE J. Solid State Circuits, 53 (9): 2500-2511 (2018)Sense amplifier offset cancellation and replica timing calibration for high-speed SRAMs., , , , and . LASCAS, page 1-5. IEEE, (2018)Tracking energy efficiency of near-threshold design using process variation control techniques., , , and . NEWCAS, page 233-236. IEEE, (2014)