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A sparse matrix vector multiply accelerator for support vector machine.

, , and . CASES, page 109-116. IEEE, (2015)

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WRPN: Wide Reduced-Precision Networks., , , and . CoRR, (2017)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC., , , , , , , , , and 1 other author(s). FPL, page 106-110. IEEE Computer Society, (2018)High performance binary neural networks on the Xeon+FPGA™ platform., , , , , , and . FPL, page 1-4. IEEE, (2017)Customizable FPGA OpenCL matrix multiply design template for deep neural networks., , , , , , , and . FPT, page 259-262. IEEE, (2017)Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI., , , , , , , , , and 6 other author(s). FPGA, page 119. ACM, (2019)SE1: What Technologies Will Shape the Future of Computing?, , , , , , , , , and . ISSCC, page 537-538. IEEE, (2021)A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study., , , , , , , , , and . FPGA, page 107-116. ACM, (2018)Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy., and . ICLR (Poster), OpenReview.net, (2018)A sparse matrix vector multiply accelerator for support vector machine., , and . CASES, page 109-116. IEEE, (2015)WRPN: Wide Reduced-Precision Networks., , , and . ICLR (Poster), OpenReview.net, (2018)