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Disambiguation of "Khafaji, Mohammad Mahdi"

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A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment.

, , , and . SoCC, page 278-283. IEEE, (2019)

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Mohammad Mahdi Khafaji

Mohammad Mahdi Motazacker

Shahla Mahdizadeh

Berie Mahdi

Nadja Mahdi

 

Other publications of authors with the same name

A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (3): 229-233 (2016)A 1-pJ/bit 80-Gb/s $2^15-1$ PRBS Generator With a Modified Cherry-Hooper Output Driver., , and . IEEE J. Solid State Circuits, 54 (7): 2059-2069 (2019)A 10-Gb/s 20-ps Delay-Range Digitally Controlled Differential Delay Element in 45-nm SOI CMOS., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (5): 1233-1237 (2019)4×40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS., , , , , , , , , and 6 other author(s). OFC, page 1-3. IEEE, (2018)A 90 μW, 2.5 GHz high linearity programmable delay cell for signal duty-cycle adjustment., , , and . SoCC, page 278-283. IEEE, (2019)Modified analytical model for subthreshold current in short channel MOSFET's., , and . IEICE Electron. Express, 4 (3): 114-120 (2007)A 16 mW 250 ps Double-Hit-Resolution Input-Sampled Time-to-Digital Converter in 45-nm CMOS., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (5): 562-566 (2018)A 1-60 GHz 9.6 mW 0.18 V Output-Swing Static Clock Divider Circuit in 45-nm SOI CMOS., , , , and . ICECS, page 41-44. IEEE, (2018)A 0.93 pJ/bit Controlled Capacitor-Charge 2-bit Pulsewidth Demodulator in 45-nm RFSOI CMOS., , , , and . NEWCAS, page 1-4. IEEE, (2019)A 2.8 pJ/bit 10 Gb/s Delayed-Phase-Select 2-bit Pulsewidth Modulator in 45-nm SOI CMOS., , , , and . NEWCAS, page 1-4. IEEE, (2019)