Author of the publication

17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI.

, , , , , and . ISSCC, page 310-312. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore's Law., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (4): 653-678 (2018)Performance evaluation of the low-voltage CML D-latch topology., , and . Integr., 36 (4): 191-209 (2003)Comparative soft error evaluation of layout cells in FinFET technology., , and . Microelectron. Reliab., 54 (9-10): 2300-2305 (2014)Analysis and comparison on full adder block in submicron technology., and . IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 806-823 (2002)Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (5): 725-736 (2011)Drop-In Energy-Performance Range Extension in Microcontrollers Beyond VDD Scaling., , and . A-SSCC, page 125-128. IEEE, (2019)Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial.. IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (1): 3-29 (2012)Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (10): 3338-3348 (2018)Power-Aware Design of Nanometer MCML Tapered Buffers., and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (1): 16-20 (2008)Low-hardware complexity PRBGs based on a piecewise-linear chaotic map., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (5): 329-333 (2006)