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Disambiguation of "Khayatzadeh, Mahmood"

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17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI.

, , , , , and . ISSCC, page 310-312. IEEE, (2016)

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Mahmood Saiyadpour

Athar Mahmood

Mahmood Haiaty

Talat Mahmood

Mahmood Mahmood Ali Barzani

 

Other publications of authors with the same name

All-digital SoC thermal sensor using on-chip high order temperature curvature correction., , , , , and . CICC, page 1-4. IEEE, (2015)A 0.7-V 17.4-µW 3-Lead Wireless ECG SoC., , , , and . IEEE Trans. Biomed. Circuits Syst., 7 (5): 583-592 (2013)iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor., , , , , , , and . IEEE J. Solid State Circuits, 53 (2): 619-631 (2018)13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS., , , , and . ISSCC, page 244-245. IEEE, (2014)8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor., , , , , , , and . ISSCC, page 160-162. IEEE, (2016)A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS., , , , and . VLSIC, page 270-. IEEE, (2015)A 0.7-V 17.4-µW 3-lead wireless ECG SoC., , , , and . BioCAS, page 344-347. IEEE, (2012)17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI., , , , , and . ISSCC, page 310-312. IEEE, (2016)Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline., and . IEEE Trans. Very Large Scale Integr. Syst., 22 (5): 971-982 (2014)