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Synthesis of VLSI architectures for tree-structured image coding.

, , and . ICIP (2), page 999-1002. IEEE Computer Society, (1996)

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Edge-adaptive local min/max nonlinear filter-based shoot suppression., and . IEEE Trans. Consumer Electronics, 52 (3): 1107-1111 (2006)Synthesis of VLSI architectures for tree-structured image coding., , and . ICIP (2), page 999-1002. IEEE Computer Society, (1996)A decoupled architecture for multi-format decoder., and . IEICE Electron. Express, 5 (18): 705-710 (2008)Parallel implementation of a financial application on a GPU., , , and . ICIS, volume 403 of ACM International Conference Proceeding Series, page 1136-1141. ACM, (2009)Synthesis of memory-based VLSI architectures for discrete wavelet transforms., , and . EUSIPCO, page 1-4. IEEE, (1996)Quarter-pel Interpolation Architecture in H.264/AVC Decoder., , and . IPC, page 224-227. IEEE Computer Society, (2007)A fast and area-efficient VLSI architecture for embedded image coding., and . ICIP (3), page 452-455. IEEE Computer Society, (1995)Register array-based VLSI architecture of H.265/HEVC loop filter.. IEICE Electron. Express, 10 (7): 20130161 (2013)High performance VLSI design of run_before for H.264/AVC CAVLD., , , and . IEICE Electron. Express, 8 (12): 950-955 (2011)A General Framework for Synthesis of Data Format Converters., and . ICPP (2), page 197-200. CRC Press, (1994)