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Compact Modeling of Channel-Resistance Effects in Reconfigurable Field-Effect Transistors., , , , , , , , , and . MIXDES, page 33-39. IEEE, (2022)Single Transistor Analog Building Blocks: Exploiting Back-Bias Reconfigurable Devices., , , , and . NEWCAS, page 1-5. IEEE, (2023)Nano Security: From Nano-Electronics to Secure Systems., , , , , , , , , and 13 other author(s). DATE, page 1334-1339. IEEE, (2021)Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates., , and . IEEE Embed. Syst. Lett., 14 (2): 107-110 (2022)Reconfigurable nanowire electronics - Device principles and circuit prospects., , , , , and . ESSDERC, page 246-251. IEEE, (2013)A wired-AND transistor: Polarity controllable FET with multiple inputs., , , , , , , , , and 3 other author(s). DRC, page 1-2. IEEE, (2018)Evaluation of Schottky barrier height at Silicide/Silicon interface of a Silicon Nanowire with Modulation Acceptor Doped Dielectric Shell., , , , , and . DRC, page 1-2. IEEE, (2023)A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs., , , , , , , , , and . DATE, page 605-608. IEEE, (2018)Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (3): 560-572 (2019)Quantitative Characterization of Reconfigurable Transistor Logic Gates., , , , , , and . IEEE Access, (2020)