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Disambiguation of "Tajalli, Armin"

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Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit.

, , , and . DATE, page 258-263. IEEE Computer Society, (2005)

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Robert Armin

Gerhard Arminger

Peter Armin

Armin Heller

Armin Mareske

 

Other publications of authors with the same name

A Controllable KVCO Ring VCO Topology., and . MWSCAS, page 732-736. IEEE, (2021)A 0.12-V 200-Hz-BW 10-Bit ADC Using Quad-Channel VCO and Interpolation Linearization., , , , , and . A-SSCC, page 1-3. IEEE, (2023)Design trade-offs in ultra-low-power CMOS and STSCL digital systems., and . ECCTD, page 544-547. IEEE, (2011)A low-power, multichannel gated oscillator-based CDR for short-haul applications., , , and . ISLPED, page 107-110. ACM, (2005)Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits., , , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 21-30. Springer, (2008)A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology., , , and . ESSCIRC, page 193-196. IEEE, (2005)A duty cycle control circuit for high speed applications., , and . ISCAS (1), page 781-784. IEEE, (2004)A Power Optimized Base-Band Circuitry for the Low-IF Receivers., , and . ISCAS, page 1693-1696. IEEE, (2007)A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS., , and . VLSIC, page 180-. IEEE, (2015)A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI., , and . CICC, page 1-2. IEEE, (2024)