Author of the publication

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit.

, , , and . DATE, page 258-263. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A high dynamic range CMOS variable gain filter for ADSL., and . ISCAS (4), page 257-260. IEEE, (2002)A technique to suppress tail current flicker noise in CMOS LC VCOs., , , and . ISCAS, IEEE, (2006)A compact, low power, fully integrated clock frequency doubler., , and . ICECS, page 563-566. IEEE, (2003)Design and optimization of a high PSRR CMOS bandgap voltage reference., , , and . ISCAS (1), page 45-48. IEEE, (2004)A Tree-Structured LoRa Network for Energy Efficiency., , and . IEEE Internet Things J., 8 (7): 6002-6011 (2021)A fractional delay-locked loop for on chip clock generation applications., , and . ASP-DAC, page 1300-1309. ACM Press, (2005)Design considerations for a 1.5-V, 10.7-MHz bandpass gm-C filter in a 0.6µm standard CMOS technology., and . ISCAS (1), page 521-524. IEEE, (2003)A low-power subscriber line interface circuit in a high-voltage CMOS technology., , and . ISCAS (5), page 409-412. IEEE, (2002)A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity., , , and . ISCAS (1), page 349-352. IEEE, (2004)A 1.5 v high-speed class AB operational amplifier for high-resolution high-speed pipelined A/D converters., , , and . ISCAS (1), page 273-276. IEEE, (2003)