( en | de | ru )

 

Disambiguation of "Nguyen-Ly, Thien Truong"

Author of the publication

copydeleteadd this publication to your clipboard
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders.

, , , , , and . CoRR, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chu Thien Truong

Thien Nguyen

Thu-Ly Truong

Nguyen Truong

Nguyen Thien Nhan

 

Other publications of authors with the same name

Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (3): 508-521 (2018)Efficient Hardware Implementations of LDPC Decoders, through Exploiting Impreciseness in Message-Passing Decoding Algorithms. (Mise en oeuvre matérielle de décodeurs LDPC haut débit, en exploitant la robustesse du décodage par passage de messages aux imprécisions de calcul).. Cergy-Pontoise University, France, (2017)Design and Implementation of a SoPC System for Speech Recognition., , , and . MUE, volume 240 of Lecture Notes in Electrical Engineering, page 1197-1203. Springer, (2013)An Annihilating Filter-Based DOA Estimation for Uniform Linear Array., , and . ACOMPA, page 80-85. IEEE, (2022)Code-aware quantizer design for finite-precision min-sum decoders., , , and . BlackSeaCom, page 1-5. IEEE, (2016)Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders., , , , , and . CoRR, (2017)Non-surjective finite alphabet iterative decoders., , , , , and . ICC, page 1-6. IEEE, (2016)Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units., , , , , and . DSD, page 230-237. IEEE Computer Society, (2016)High-Performance and Low-Complexity Decoding Algorithms for 5G Low-Density Parity-Check Codes., , and . J. Commun., 17 (5): 358-364 (2022)High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders., , , and . ICC Workshops, page 961-966. IEEE, (2017)