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pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.

R. Kho, D. Boursin, M. Brox, P. Gregorius, H. Hoenigschmid, B. Kho, S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller, P. Petkov, M. Plan, M. Richter, I. Russell, K. Schiller, R. Schneider, K. Swaminathan, B. Weber, J. Weber, I. Bormann, F. Funfrock, M. Gjukic, W. Spirkl, H. Steffens, J. Weller, and T. Hein. IEEE J. Solid State Circuits, 45 (1): 120-133 (2010)

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Peter Gregorius

Gregorius

Ruth Gregorius

Other publications of authors with the same name

A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS.N. Dalt, E. Thaller, P. Gregorius, and L. Gazsi. IEEE J. Solid State Circuits, 40 (7): 1482-1490 (2005)75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques.R. Kho, D. Boursin, M. Brox, P. Gregorius, H. Hoenigschmid, B. Kho, S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller and 16 other author(s). ISSCC, page 134-135. IEEE, (2009)Adaptive Equalizer Training for High-Speed Low-Power Communication Systems.Y. Fang, L. Chen, A. Jaiswal, K. Hofmann, and P. Gregorius. DSD, page 745-751. IEEE Computer Society, (2013)A 10 GbE TCP/IP hardware stack as part of a protocol acceleration platform.U. Langenbach, A. Berthe, B. Traskov, S. Weide, K. Hofmann, and P. Gregorius. ICCE-Berlin, page 381-384. IEEE, (2013)Hardware architecture of an Internet Protocol Version 6 processor.B. Traskov, U. Langenbach, K. Hofmann, and P. Gregorius. SoCC, page 198-203. IEEE, (2014)A low jitter triple-band digital LC PLL in 130nm CMOS.N. Dalt, E. Thaller, P. Gregorius, and L. Gazsi. ESSCIRC, page 371-374. IEEE, (2004)A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.R. Kho, D. Boursin, M. Brox, P. Gregorius, H. Hoenigschmid, B. Kho, S. Kieser, D. Kehrer, M. Kuzmenka, U. Moeller and 16 other author(s). IEEE J. Solid State Circuits, 45 (1): 120-133 (2010)Cascading Techniques for a High-Speed Memory Interface.Z. Gu, P. Gregorius, D. Kehrer, L. Neumann, E. Neuscheler, T. Rickes, H. Ruckerbauer, R. Schledz, M. Streibl, and J. Zielbauer. ISSCC, page 234-599. IEEE, (2007)Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication Systems.A. Jaiswal, Y. Fang, P. Gregorius, and K. Hofmann. DSD, page 752-758. IEEE Computer Society, (2013)

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Disambiguation of "Gregorius, Peter"

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A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.

Please choose a person to relate this publication to

Peter Gregorius

Peter Gregorius

Gregorius

Gregorius

Ruth Gregorius

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Gregorius, Peter"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.

Please choose a person to relate this publication to

Peter Gregorius

Peter Gregorius

Gregorius

Gregorius

Ruth Gregorius

Other publications of authors with the same name

Disambiguation

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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.