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Disambiguation of "Kim, Jae-Joon"

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A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies.

, and . IEEE Trans. Very Large Scale Integr. Syst., 14 (5): 549-552 (2006)

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Joon-Young Kim

Nam-Joon Kim

Man Joon Kim

Joon-Soon Kim

Hyun-Joon Kim

 

Other publications of authors with the same name

Highly improved SNR differential sensing method using parallel operation signaling for touch screen application., , , and . A-SSCC, page 157-160. IEEE, (2014)A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS., , , and . ISSCC, page 388-389. IEEE, (2008)A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (3): 349-357 (2005)One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 600-612 (2016)Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator., , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (1): 138-146 (2019)Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices., , , , , , and . Microelectron. J., 38 (8-9): 931-941 (2007)A CMOS single-chip wireless solution with an adaptive purity-control scheme against ISM-band interferences., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (4): 269-273 (2006)OPTIMUS: OPTImized matrix MUltiplication Structure for Transformer neural network accelerator., , , , and . MLSys, mlsys.org, (2020)Technology-circuit co-design of asymmetric SRAM cells for read stability improvement., , and . CICC, page 1-4. IEEE, (2010)A forward body-biased low-leakage SRAM cache: device and architecture considerations., , , and . ISLPED, page 6-9. ACM, (2003)