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Disambiguation of "Wong, Stephan"

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The MOLEN rho-mu-Coded Processor.

, , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 275-285. Springer, (2001)

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Walter Wong

Limsoon Wong

Hoi-Ming Wong

Yasert Wongthonglua

Wei-chwen Wong

 

Other publications of authors with the same name

Machine Learning-Based Processor Adaptability Targeting Energy, Performance, and Reliability., , , , and . ISVLSI, page 158-163. IEEE, (2019)Configurable, low-power design for inverse integer transform in H.264/AVC., , and . FIT, page 32. ACM, (2010)MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory., , , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (3): 44:1-44:24 (2022)A Case for Genome Analysis Where Genomes Reside., , and . SAMOS, volume 14385 of Lecture Notes in Computer Science, page 453-458. Springer, (2023)A just-in-time modulo scheduling for virtual coarse-grained reconfigurable architectures., , , , , and . ICSAMOS, page 188-195. IEEE, (2013)Systematic Customization of On-Chip Crossbar Interconnects., , , and . ARC, volume 4419 of Lecture Notes in Computer Science, page 61-72. Springer, (2007)A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC., , , and . ESTIMedia, page 18-27. IEEE Computer Society, (2009)A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs., , , , , , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 499-510. Springer, (2018)A run-time graph-based Polynomial Placement and routing algorithm for virtual FPGAS., , , , , and . FPL, page 1-8. IEEE, (2013)Customizing Reconfigurable On-Chip Crossbar Scheduler., , , and . ASAP, page 210-215. IEEE Computer Society, (2007)