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Disambiguation of "Sartor, Anderson Luiz"

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Machine Learning-Based Processor Adaptability Targeting Energy, Performance, and Reliability.

, , , , and . ISVLSI, page 158-163. IEEE, (2019)

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Thomas Luiz

Janos Sartor

Christina Sartor

Ralph Sartor

Wolfgang Sartor

 

Other publications of authors with the same name

A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs., , , , , , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 499-510. Springer, (2018)Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance., , , , and . CF, page 54-61. ACM, (2018)Machine Learning-Based Processor Adaptability Targeting Energy, Performance, and Reliability., , , , and . ISVLSI, page 158-163. IEEE, (2019)Optimized Use of Parallel Programming Interfaces in Multithreaded Embedded Architectures., , , and . ISVLSI, page 410-415. IEEE Computer Society, (2015)A fast and accurate hybrid fault injection platform for transient and permanent faults., , and . Des. Autom. Embed. Syst., 23 (1-2): 3-19 (2019)BRAM-based function reuse for multi-core architectures in FPGAs., , , and . Microprocess. Microsystems, (2018)DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability., , , , , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 367-378. Springer, (2018)How Programming Languages and Paradigms Affect Performance and Energy in Multithreaded Applications., , , , and . SBESC, page 71-78. IEEE Computer Society, (2016)Multi-architecture profiler for Android., and . Int. J. High Perform. Syst. Archit., 7 (1): 41-55 (2017)A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors., , , , , and . ISVLSI, page 485-490. IEEE Computer Society, (2015)