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Disambiguation of "Giterman, Robert"

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Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros.

, , , , and . IEEE Access, (2021)

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Robert Klöfkorn

Numerics for evolution equations: a general interface based design concept. Uni Freiburg, (2009)

Robert Wille

Towards a design flow for reversible logic. Uni Bremen, (2009)

Robert Braun

Referenzmodellierung: Grundlegung und Evaluation der Technik des Modell-Konfigurationsmanagements. TU Dresden, (2010)

Robert Wagner

Inkrementelle Modellsynchronisation. Uni Paderborn, (2009)

Robert Zangenfeind

Das Bedeutung-Text-Modell: Wörterbuch und Grammatik einer integralen Sprachbeschreibung. Uni München, (2009)
 

Other publications of authors with the same name

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection., , and . IEEE Access, (2019)Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (1): 358-362 (2016)Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space., , , , , and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (4): 1207-1217 (2020)Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros., , , , and . IEEE Access, (2021)Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (4): 259-263 (2014)Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique., , , and . ISCAS, page 1-5. IEEE, (2020)4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes., , , , and . ISCAS, page 2177-2180. IEEE, (2014)A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design., , , , and . ISCAS, page 1006-1009. IEEE, (2016)Gain-Cell Embedded DRAM-Based Physical Unclonable Function., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (12): 4208-4218 (2018)Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads., , , , , , , , and . IEEE Access, (2021)