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Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism., , , , , , , , and . CoRR, (2016)Performance analysis and validation of the picoJava processor., and . IEEE Micro, 19 (3): 66-72 (1999)Open Standard Content Cookies: Utility vs. Privacy., , , and . WebNet, AACE, (1997)Characterizing and Mitigating Soft Errors in GPU DRAM., , , , , , , , and . MICRO, page 641-653. ACM, (2021)A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch., , , , and . MICRO, page 247-257. IEEE Computer Society, (2012)What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study., , , , , , , , , and 2 other author(s). SIGMETRICS (Abstracts), page 110. ACM, (2018)Reducing Data Transfer Energy by Exploiting Similarity within a Data Transaction., , and . HPCA, page 40-51. IEEE Computer Society, (2018)GPUDet: a deterministic GPU architecture., , , , and . ASPLOS, page 1-12. ACM, (2013)Managing DRAM Latency Divergence in Irregular GPGPU Applications., , , , and . SC, page 128-139. IEEE Computer Society, (2014)Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks., , , , and . CoRR, (2017)