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Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models.

, , , , , and . ISVLSI, page 241-246. IEEE Computer Society, (2009)

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Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling., , , , and . MTV, page 3-8. IEEE Computer Society, (2009)Accelerating multi-party scheduling for transaction-level modeling., , , , , , and . ACM Great Lakes Symposium on VLSI, page 339-344. ACM, (2009)An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs., , , and . ISQED, page 377-381. IEEE Computer Society, (2009)Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation., , and . IOLTW, page 65-. IEEE Computer Society, (2001)Portable simulation/emulation stimulus on an industrial-strength SoC., , , , , and . ITC, page 1. IEEE Computer Society, (2009)Controlling State Explosion in Static Simulation by Selective Composition., , , , , and . VLSI Design, page 226-231. IEEE Computer Society, (1999)Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models., , , , , and . ISVLSI, page 241-246. IEEE Computer Society, (2009)Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification., , , , , and . MTV, page 7-10. IEEE Computer Society, (2003)A genetic approach to automatic bias generation for biased random instruction generation., , , , and . CEC, page 442-448. IEEE, (2001)