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Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures., , and . ASP-DAC, page 692-699. IEEE, (2014)Multi-context non-volatile content addressable memory using magnetic tunnel junctions., , , and . NANOARCH, page 103-108. ACM, (2016)SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 13 (1): 150-164 (March 2023)Impact of Resistive-Bridge Defects in TAS-MRAM Architectures., , , , , , , , and . Asian Test Symposium, page 125-130. IEEE Computer Society, (2012)A built-in IDDQ testing circuit., , , , , and . ESSCIRC, page 471-474. IEEE, (2005)InMRAM: Introductory course on Magnetic Random Access Memories for microelectronics students and engineers., , and . EWME, page 21-25. IEEE, (2014)TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA., , , , and . ACM Trans. Reconfigurable Technol. Syst., 2 (2): 8:1-8:19 (2009)A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses., , , , , , , , , and . CoRR, (2023)SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures., , , , , and . ACM Trans. Embed. Comput. Syst., 22 (5s): 131:1-131:25 (October 2023)Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation., , , , , and . DATE, page 1-6. IEEE, (2023)