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Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory.

, , and . APCCAS, page 1301-1304. IEEE, (2006)

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A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)On-demand memory sub-system for multi-core SoCs., , and . SoCC, page 122-127. IEEE, (2011)An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions., , , and . SoCC, page 19-23. IEEE, (2011)All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction., , , , , , and . VLSI-DAT, page 1-4. IEEE, (2015)An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications., , , , , and . ISCAS, page 1370-1373. IEEE, (2015)A fully-differential subthreshold SRAM cell with auto-compensation., and . APCCAS, page 1771-1774. IEEE, (2008)Low quiescent current variable output digital controlled voltage regulator., and . ISCAS, page 609-612. IEEE, (2010)A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM., , and . ISCAS, IEEE, (2006)Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application., , , , and . SoCC, page 18-23. IEEE, (2016)Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory., , and . APCCAS, page 1301-1304. IEEE, (2006)