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Disambiguation of "Miyahara, Masaya"

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An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation.

, , , , , , , , , , , , , , and . A-SSCC, page 109-112. IEEE, (2016)

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Other publications of authors with the same name

A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers., , and . A-SSCC, page 65-68. IEEE, (2016)Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (2): 476-484 (2015)SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier., and . ASICON, page 24-27. IEEE, (2017)A 12-bit interpolated pipeline ADC using body voltage controlled amplifier., , and . NEWCAS, page 1-4. IEEE, (2013)A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers., , , , and . CICC, page 1-4. IEEE, (2013)20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding., , , , , , , , , and 4 other author(s). ISSCC, page 346-347. IEEE, (2014)SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier., and . IEICE Electron. Express, (2018)A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier., , , and . VLSI Circuits, page 115-116. IEEE, (2018)A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique., , and . ISCAS, page 21-24. IEEE, (2011)An analysis on a pseudo-differential dynamic comparator with load capacitance calibration., , and . ASICON, page 461-464. IEEE, (2011)