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Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design., , и . FPGA, стр. 247. ACM, (1999)Critical-path-aware high-level synthesis with distributed controller for fast timing closure., и . ACM Trans. Design Autom. Electr. Syst., 19 (2): 16:1-16:29 (2014)Entry control in network-on-chip for memory power reduction., , и . ISLPED, стр. 171-176. ACM, (2008)Coarse-grained reconfigurable architecture for multiple application domains: a case study., , , , , , и . ICHIT, том 321 из ACM International Conference Proceeding Series, стр. 546-553. ACM, (2009)Lower-bits cache for low power STT-RAM caches., и . ISCAS, стр. 480-483. IEEE, (2012)Optimal mapping of program overlays onto many-core platforms with limited memory capacity., , и . Des. Autom. Embed. Syst., 21 (3-4): 173-194 (2017)Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems., и . CASES, стр. 230-237. ACM, (2004)Binary acceleration using coarse-grained reconfigurable architecture., , и . SIGARCH Comput. Archit. News, 38 (4): 33-39 (2010)A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections., и . NOCS, стр. 1-2. IEEE, (2013)A new stochastic mutiplier for deep neural networks., , и . ISOCC, стр. 46-47. IEEE, (2017)