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Scan-controlled pulse flip-flops for mobile application processors., , , , , , , , , and 1 other author(s). ISCAS, page 769-772. IEEE, (2013)Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling., , , , , , , , , and 1 other author(s). ISCAS, page 1-5. IEEE, (2018)Performance-oriented technology mapping for LUT-based FPGA's., and . IEEE Trans. Very Large Scale Integr. Syst., 3 (2): 323-327 (1995)A combined hierarchical placement algorithm., , , , , , and . ICCAD, page 164-169. IEEE Computer Society / ACM, (1993)Performance-driven circuit partitioning for prototyping by using multiple FPGA chips., , and . ASP-DAC, ACM, (1995)A performance-driven logic emulation system: FPGA network design and performance-driven partitioning., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (5): 560-568 (1996)Dynamic Differential Flip-Flop without Explicit Output Latching Stage for High-Speed SoC., , , , , and . ICECS, page 1-4. IEEE, (2021)23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor., , , , , , , , , and 14 other author(s). ISSCC, page 1-3. IEEE, (2015)Single-ended D flip-flop with implicit scan mux for high performance mobile AP., , , , , , , , , and 2 other author(s). SoCC, page 91-95. IEEE, (2016)A simple yet effective technique for partitioning., and . IEEE Trans. Very Large Scale Integr. Syst., 1 (3): 380-386 (1993)