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Disambiguation of "Kaeriyama, Shunichi"

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A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems.

, , , , , , , , , , , , , , , , , , and . ISSCC, page 358-359. IEEE, (2009)

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Other publications of authors with the same name

Solid-Electrolyte Nanometer Switch., , , , , , , , and . IEICE Trans. Electron., 89-C (11): 1492-1498 (2006)A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems., , , , , , , , , and 9 other author(s). ISSCC, page 358-359. IEEE, (2009)A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability., , and . ISSCC, page 174-594. IEEE, (2007)A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 44 (12): 3568-3579 (2009)Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic., , and . J. Multiple Valued Log. Soft Comput., 11 (5-6): 619-632 (2005)High-speed wireline transceivers and clocking., and . CICC, page 1-2. IEEE, (2012)Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links: Wireline subcommittee., and . ISSCC, page 50-51. IEEE, (2015)A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests., , and . IEICE Trans. Electron., 94-C (1): 102-109 (2011)A nonvolatile programmable solid-electrolyte nanometer switch., , , , , , , , and . IEEE J. Solid State Circuits, 40 (1): 168-176 (2005)Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic., , and . ISMVL, page 438-446. IEEE Computer Society, (2000)