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12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.

J. Chang, Y. Chen, W. Chan, S. Singh, H. Cheng, H. Fujiwara, J. Lin, K. Lin, J. Hung, R. Lee, H. Liao, J. Liaw, Q. Li, C. Lin, M. Chiang, and S. Wu. ISSCC, page 206-207. IEEE, (2017)

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Esther Fujiwara

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A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.K. Nii, M. Yabuuchi, H. Fujiwara, Y. Tsukamoto, Y. Ishii, T. Matsumura, and Y. Matsuda. ISQED, page 438-441. IEEE, (2013)3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications.Y. Osada, T. Nakazato, K. Nii, J. Liaw, S. Wu, Q. Li, H. Fujiwara, H. Liao, and T. Chang. VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications.C. Lee, C. Lu, C. Lee, H. Mori, H. Fujiwara, Y. Shih, T. Chou, Y. Chih, and T. Chang. VLSI Technology and Circuits, page 24-25. IEEE, (2022)34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.H. Fujiwara, H. Mori, W. Zhao, K. Khare, C. Lee, X. Peng, V. Joshi, C. Chuang, S. Hsu, T. Hashizume and 13 other author(s). ISSCC, page 572-574. IEEE, (2024)A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.H. Noguchi, Y. Iguchi, H. Fujiwara, Y. Morita, K. Nii, H. Kawaguchi, and M. Yoshimoto. ISVLSI, page 107-112. IEEE Computer Society, (2007)A stable chip-ID generating physical uncloneable function using random address errors in SRAM.H. Fujiwara, M. Yabuuchi, Y. Tsukamoto, H. Nakano, T. Owada, H. Kawai, and K. Nii. SoCC, page 143-147. IEEE, (2012)12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.J. Chang, Y. Chen, W. Chan, S. Singh, H. Cheng, H. Fujiwara, J. Lin, K. Lin, J. Hung, R. Lee and 6 other author(s). ISSCC, page 206-207. IEEE, (2017)A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures.M. Yabuuchi, Y. Tsukamoto, H. Fujiwara, M. Tanaka, S. Shinji, and K. Nii. IEEE Trans. Very Large Scale Integr. Syst., 26 (11): 2335-2344 (2018)A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications.T. Chang, Y. Chen, W. Chan, H. Cheng, P. Wang, Y. Lin, H. Fujiwara, R. Lee, H. Liao, P. Wang and 2 other author(s). IEEE J. Solid State Circuits, 56 (1): 179-187 (2021)17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.H. Fujiwara, L. Wang, Y. Chen, K. Lin, D. Sun, S. Wu, J. Liaw, C. Lin, M. Chiang, H. Liao and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)

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Disambiguation of "Fujiwara, Hidehiro"

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12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.

Please choose a person to relate this publication to

Esther Fujiwara

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Disambiguation of "Fujiwara, Hidehiro"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.

Please choose a person to relate this publication to

Esther Fujiwara

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Disambiguation

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12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.