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Disambiguation of "Yoshimoto, Masahiko"

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A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.

, , , , , , and . ISVLSI, page 107-112. IEEE Computer Society, (2007)

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Masahiko Isaji

Kei Yoshimoto

 

Other publications of authors with the same name

Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential., , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2011)A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM., , , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2016)A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search., , , , , , , , , and . IEEE J. Solid State Circuits, 30 (12): 1502-1509 (December 1995)A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme., , , , , , , , and . IEICE Trans. Electron., 98-C (4): 333-339 (2015)A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation., , , , , , , , , and 4 other author(s). IEICE Trans. Electron., 97-C (4): 332-341 (2014)Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes., , , , , , , and . IEICE Trans. Commun., 95-B (1): 178-188 (2012)Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks., , , , , and . IEICE Trans. Commun., 91-B (11): 3489-3498 (2008)A Dependable SRAM with 7T/14T Memory Cells., , , , , and . IEICE Trans. Electron., 92-C (4): 423-432 (2009)A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer., , , , , , , , and . IEICE Trans. Electron., 91-C (4): 465-478 (2008)VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition., , , , , and . IEICE Trans. Electron., 94-C (4): 458-467 (2011)