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A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.

S. Li, F. Spagna, J. Chen, X. Wang, L. Tong, S. Gowder, W. Jia, R. Nicholson, S. Iyer, R. Song, L. Li, M. hung Chen, A. Tran, M. Vita, D. Govindrajan, M. Pasquarella, D. Bradley, F. Verdico, M. Duwe, E. Lee, and M. Wigton. A-SSCC, page 5-8. IEEE, (2018)

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Li Li

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The Implementation of a VHDL-AMS to SPICE Converter.S. Li, B. Okoon, M. Hella, M. Ismail, and M. Rubeiz. J. VLSI Signal Process., 22 (2): 113-121 (1999)A Geometric Sufficient Condition for Contact Wrench Feasibility.S. Li, H. Chen, W. Zhang, and P. Wensing. IEEE Robotics Autom. Lett., 7 (4): 12411-12418 (2022)Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling.S. Li, C. Tsai, E. Soenen, F. Lee, and C. Hsieh. A-SSCC, page 1-3. IEEE, (2021)A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.S. Li, F. Spagna, J. Chen, X. Wang, L. Tong, S. Gowder, W. Jia, R. Nicholson, S. Iyer, R. Song and 11 other author(s). A-SSCC, page 5-8. IEEE, (2018)Quadruped Robot Hopping on Two Legs.S. Li, H. Chen, W. Zhang, and P. Wensing. IROS, page 7448-7455. IEEE, (2021)Interconnect in the Era of 3DIC.S. Li, M. Lin, W. Chen, and C. Tsai. CICC, page 1-5. IEEE, (2022)A Lower Power CMOS Micromixer for GHz Wireless Applications.Y. Wu, S. Li, M. Ismail, and H. Olsson. VLSI, volume 162 of IFIP Conference Proceedings, page 35-46. Kluwer, (1999)Clock generation for a 32nm server processor with scalable cores.S. Li, A. Krishnakumar, E. Helder, R. Nicholson, and V. Jia. ISSCC, page 82-83. IEEE, (2011)Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application.S. Li, Y. Wu, C. Shi, and M. Ismail. VLSI, volume 162 of IFIP Conference Proceedings, page 1-10. Kluwer, (1999)A 22 nm 15-Core Enterprise Xeon® Processor Family.S. Rusu, H. Muljono, D. Ayers, S. Tam, W. Chen, A. Martin, S. Li, S. Vora, R. Varada, and E. Wang. IEEE J. Solid State Circuits, 50 (1): 35-48 (2015)

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Disambiguation of "Li, Shenggao"

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A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.

Please choose a person to relate this publication to

Li Li

Li Li

Li Li

Li Li

Li Li

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Li, Shenggao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.

Please choose a person to relate this publication to

Li Li

Li Li

Li Li

Li Li

Li Li

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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APA
Chicago
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A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.