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On efficient generation of instruction sequences to test for delay defects in a processor., , , and . ACM Great Lakes Symposium on VLSI, page 279-284. ACM, (2008)Quantitative evaluation of soft error injection techniques for robust system design., , , , and . DAC, page 101:1-101:10. ACM, (2013)A Framework for Distributed VLSI Simulation on a Network of Workstations., and . Simulation, 60 (2): 95-104 (1993)ESIFT: Efficient System for Error Injection., , and . IOLTS, page 201-206. IEEE, (2018)Delay Constrained Register Transfer Level Dynamic Power Estimation., , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 36-46. Springer, (2006)Property Checking via Structural Analysis., , and . CAV, volume 2404 of Lecture Notes in Computer Science, page 151-165. Springer, (2002)A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems., and . ISLPED, page 391-396. IEEE/ACM, (2011)Research in Reliable VLSI Architectures at the University of Illinois.. FJCC, page 890-893. IEEE Computer Society, (1986)Design of Test Pattern Generators for Built-In Test., , and . ITC, page 315-319. IEEE Computer Society, (1984)Test Generation for Microprocessors., and . IEEE Trans. Computers, 29 (6): 429-441 (1980)