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Distributed replay protocol for distributed uniprocessors., , , , , , и . ICS, стр. 3-14. ACM, (2012)FACRA: Flexible-Core Architecture Chip Resource Abstractor., , , , , , и . PDCAT, стр. 440-447. IEEE Computer Society, (2010)CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors., , , , , и . ICCAD, стр. 1-8. IEEE, (2013)TEMP: thread batch enabled memory partitioning for GPU., , , , , , и . DAC, стр. 65:1-65:6. ACM, (2016)Heterogeneous systems with reconfigurable neuromorphic computing accelerators., , , , , , и . ISCAS, стр. 125-128. IEEE, (2016)An efficient STT-RAM-based register file in GPU architectures., , , , и . ASP-DAC, стр. 490-495. IEEE, (2015)Prefetching techniques for STT-RAM based last-level cache in CMP systems., , , , и . ASP-DAC, стр. 67-72. IEEE, (2014)Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory., , , , и . DAC, стр. 196:1-196:6. ACM, (2014)Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators., , , , , , , , , и 1 other автор(ы). IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (5): 617-628 (2016)Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper)., , , , , и . ISIC, стр. 124-127. IEEE, (2014)