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Disambiguation of "Yeo, Kiat Seng"

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Ultra low-power high-speed flexible Probabilistic Adder for Error-Tolerant Applications.

, , and . ISOCC, page 393-396. IEEE, (2011)

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Zié Yeo

Inho Yeo

Fuangpet Kiativesi-Koanantakul

Sirichai Kiattavorncharoen

Vichit Kiatsrichart

 

Other publications of authors with the same name

A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter., , , , , , and . A-SSCC, page 141-144. IEEE, (2011)0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance., , , , , and . IEEE J. Solid State Circuits, 49 (7): 1487-1498 (2014)A low power millimetre-wave VCO in 0.18 µm SiGe BiCMOS technology., , , and . APCCAS, page 244-247. IEEE, (2012)2.5 A 2-to-6GHz Class-AB power amplifier with 28.4% PAE in 65nm CMOS supporting 256QAM., , and . ISSCC, page 1-3. IEEE, (2015)SiGe BiCMOS power amplifiers for 60GHz ISM band applications., , , , and . ISOCC, page 13-16. IEEE, (2011)Body-bootstrapped-buffer circuit for CMOS static power reduction., , , , and . APCCAS, page 842-845. IEEE, (2008)Low-power high-speed dual-modulus prescaler for Gb/s applications., , and . APCCAS, page 256-259. IEEE, (2012)A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4., , , , , and . VLSI-SoC, page 387-391. IEEE, (2010)An Inductorless 5-GHz Differential Dual Regulated Cross-Cascode Transimpedance Amplifier using 40 nm CMOS., , , , and . ASICON, page 1-4. IEEE, (2019)RF mixer design techniques using GaAs process., , and . ASICON, page 1013-1016. IEEE, (2017)