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A shorted global clock design for multi-GHz 3D stacked chips., , , , , and . VLSIC, page 170-171. IEEE, (2012)On-chip timing uncertainty measurements on IBM microprocessors., , , , , , , , and . ITC, page 1-7. IEEE Computer Society, (2007)POWER8 design methodology innovations for improving productivity and reducing power., , , , , , , , , and 1 other author(s). CICC, page 1-9. IEEE, (2014)A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file., , and . IEEE J. Solid State Circuits, 32 (8): 1288-1292 (1997)Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning., , and . ISPD, page 29-37. ACM, (2022)On-chip Timing Uncertainty Measurements on IBM Microprocessors., , , , , , , , and . ITC, page 1-7. IEEE Computer Society, (2008)The physical design of on-chip interconnections., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (3): 254-276 (2003)Estimating the efficiency of collaborative problem-solving, with applications to chip design., , , , , and . IBM J. Res. Dev., 47 (1): 77-88 (2003)Advances in Membrane Probe Technology., and . ITC, page 927-935. IEEE Computer Society, (1992)