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Disambiguation of "Verma, Vaibhav"

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ATCPiM: Analog to Time Coded Processing in Memory for IoT at the Edge.

, , , , and . WF-IoT, page 704-709. IEEE, (2021)

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Vishal Vaibhav

Vaibhav Agarwal

Vaibhav Karkare

Vaibhav Singh

Vaibhav Bajpai

 

Other publications of authors with the same name

EXTREM-EDGE - EXtensions To RISC-V for Energy-efficient ML inference at the EDGE of IoT., , and . Sustain. Comput. Informatics Syst., (2022)eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing., , , , and . MICRO, page 87-99. ACM, (2019)ATCPiM: Analog to Time Coded Processing in Memory for IoT at the Edge., , , , and . WF-IoT, page 704-709. IEEE, (2021)LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores., , , , , and . SOCC, page 1-6. IEEE, (2023)Back to the Future: Digital Circuit Design in the FinFET Era., , , , and . J. Low Power Electron., 13 (3): 338-355 (2017)When "things" get older: Exploring circuit aging in IoT applications., , , and . ISQED, page 296-301. IEEE, (2018)A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology., , , and . SoCC, page 304-309. IEEE, (2015)A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing., , , , and . IEEE Comput. Archit. Lett., 18 (2): 87-90 (2019)Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology., , and . VDAT, page 1-6. IEEE, (2020)Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units., , , , , and . ACM Great Lakes Symposium on VLSI, page 467-471. ACM, (2023)