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Disambiguation of "Matsuzawa, Akira"

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Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector.

, , , , and . IEICE Trans. Electron., 102-C (7): 520-529 (2019)

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Akira Hayashima

Akira Hori

Akira Satake

Akira Hayashima

Akira Yasui

 

Other publications of authors with the same name

Feedforward compensation technique for all digital phase locked loop based synthesizers., , and . ISCAS, IEEE, (2006)A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI., , , , , , and . IEICE Electron. Express, 12 (15): 20150531 (2015)A 14.3% PAE parallel class-A and AB 60GHz CMOS PA., , , and . IEICE Electron. Express, 8 (13): 1071-1074 (2011)A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration., , , , , and . IEEE J. Solid State Circuits, 49 (1): 50-60 (2014)A Study of Stability and Phase Noise of Tail Capacitive-Feedback VCOs., , and . IEICE Trans. Electron., 96-C (4): 577-585 (2013)Characterization of Crossing Transmission Line Using Two-Port Measurements for Millimeter-Wave CMOS Circuit Design., , , , , and . IEICE Trans. Electron., 98-C (1): 35-44 (2015)A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells., , , and . IEICE Trans. Electron., 101-C (4): 197-205 (2018)A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition., , and . IEICE Trans. Electron., 95-C (7): 1285-1296 (2012)A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (2): 422-433 (2013)A CMOS Smart Image Sensor LSI for Focal-Plane Compression., , , , , , , and . ASP-DAC, page 339-340. IEEE, (1998)