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Disambiguation of "Chaurasia, Rahul"

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Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics.

, and . iSES, page 153-158. IEEE, (2023)

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Priyanka Chaurasia

Rahul Gupta

Gautam Chaurasia

Neera Chaurasia

Bhagirath Chaurasia

 

Other publications of authors with the same name

Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key., , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (6): 826-839 (June 2023)Securing IP Cores for DSP Applications Using Structural Obfuscation and Chromosomal DNA Impression., and . IEEE Access, (2022)Secured Convolutional Layer IP Core in Convolutional Neural Network Using Facial Biometric., and . IEEE Trans. Consumer Electron., 68 (3): 291-306 (2022)Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs., , and . Comput. Electr. Eng., 111 (Part A): 108928 (October 2023)Security Vs Design Cost of Signature Driven Security Methodologies for Reusable Hardware IP Core., and . iSES, page 283-288. IEEE, (2022)Biometrics for Hardware Security and Trust: Discussion and Analysis., , and . IT Prof., 25 (4): 36-44 (July 2023)Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS., and . Integr., (March 2024)Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores., , , , and . Comput. Electr. Eng., (January 2023)Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis., , and . Microprocess. Microsystems, (2023)Retinal Biometric for Securing JPEG-Codec Hardware IP Core for CE Systems., and . IEEE Trans. Consumer Electron., 69 (3): 441-457 (August 2023)