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Spur Immunity in MASH-Based Fractional-N CP-PLLs With Polynomial Nonlinearities.

, and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (6): 2295-2306 (2021)

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The noise and spur delusion in fractional-N frequency synthesizer design., , , , , and . ISCAS, page 2577-2580. IEEE, (2015)A qualitative analysis of a complementary differential LC injection-locked frequency divider based on direct injection., and . ISCAS, page 1531-1534. IEEE, (2010)Simulation of the multipath performance of FM-DCSK digital communications using chaos., , and . ISCAS (4), page 568-571. IEEE, (1999)Jitter Minimization in Digital PLLs with Mid-Rise TDCs., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (3): 743-752 (2020)Analysis of Wandering Spur Patterns in a Fractional-N Frequency Synthesizer With a MASH-Based Divider Controller., and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (3): 729-742 (2020)Linear model-based testing of ADC nonlinearities., and . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (1): 213-217 (2004)The Role of Charge Pump Mismatch in the Generation of Integer Boundary Spurs in Fractional-N Frequency Synthesizers: Why Worse Can Be Better., , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (12): 862-866 (2013)Statistical Properties of First-Order Bang-Bang PLL With Nonzero Loop Delay., and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (10): 1016-1020 (2008)Influence of noise intensity on the spectrum of an oscillator., , and . IEEE Trans. Circuits Syst. II Express Briefs, 52-II (11): 789-793 (2005)Maximum Sequence Length MASH Digital Delta-Sigma Modulators., and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (12): 2628-2638 (2007)