( en | de | ru )

 

Disambiguation of "Itoh, Kiyoo"

Author of the publication

copydeleteadd this publication to your clipboard
Energy efficiency optimization for digital applications in 28nm UTBB FDSOI technology.

, , , , and . MIXDES, page 23. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Naoki Itoh

Itoh Wihardjo Surjono

 

Other publications of authors with the same name

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays., , , , and . IEICE Trans. Electron., 95-C (4): 594-599 (2012)Nanoscale Memory Repair, and . Integrated Circuits and Systems Springer, (2011)Low-voltage limitations of memory-rich nano-scale CMOS LSIs., , and . ESSCIRC, page 68-75. IEEE, (2007)0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs., , and . IEICE Trans. Electron., 95-C (4): 555-563 (2012)Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation., , , , , , and . IEICE Trans. Electron., 90-C (4): 758-764 (2007)Low-Voltage Embedded-RAM Technology: Present and Future., and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 277-288. Kluwer, (2001)Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs., , , , and . CICC, page 1-7. IEEE, (2011)A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 36 (11): 1721-1727 (2001)Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs.. PATMOS, volume 6448 of Lecture Notes in Computer Science, page 255. Springer, (2010)Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.. ISLPED, page 273-274. ACM, (2009)