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A high-efficiency strongly self-checking asynchronous datapath.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (10): 1484-1494 (2004)

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Design for Self-Checking and Self-Timed Datapath., , , and . VTS, page 417-430. IEEE Computer Society, (2003)A self-timed divider using a new fast and robust pipeline scheme., , and . IEEE J. Solid State Circuits, 36 (6): 917-923 (2001)State-Sensitive X-Filling Scheme for Scan Capture Power Reduction., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (7): 1338-1343 (2008)A high-efficiency strongly self-checking asynchronous datapath., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (10): 1484-1494 (2004)Pipelined Dataflow Architecture of a Small Processor., , , , , , and . PDPTA, page 1217-1223. CSREA Press, (1999)Pipelines in Dynamic Dual-Rail Circuits., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 701-710. Springer, (2004)A Totally Self-Checking Dynamic Asynchronous Datapath., , , and . Asian Test Symposium, page 27-32. IEEE Computer Society, (2002)Parallel Interleavers Through Optimized Memory Address Remapping.. IEEE Trans. Very Large Scale Integr. Syst., 18 (6): 978-987 (2010)