Author of the publication

Low-latency area-efficient decoding architecture for shortened reed-solomon codes.

, , and . ISOCC, page 223-226. IEEE, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Fast Successive Cancellation List Decoder for Polar Codes With an Early Stopping Criterion., and . IEEE Trans. Signal Process., 66 (18): 4971-4979 (2018)Improved Hard-Reliability Based Majority-Logic Decoding for Non-Binary LDPC Codes., and . IEEE Communications Letters, 21 (1): 230-233 (2017)Virtual Chip: Making Functional Models Work on Real Target Systems., , , , , and . DAC, page 170-173. ACM Press, (1998)Verification of a Microprocessor Using Real World Applications., , , and . DAC, page 181-184. ACM Press, (1999)Improved Successive-Cancellation Decoding of Polar Codes Based on Recursive Syndrome Decomposition., and . IEEE Communications Letters, 21 (11): 2344-2347 (2017)A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading., and . IEEE J. Solid State Circuits, 53 (11): 3327-3337 (2018)Address code generation for DSP instruction-set architectures., and . ACM Trans. Design Autom. Electr. Syst., 8 (3): 384-395 (2003)Time-Domain Joint Estimation of Fine Symbol Timing Offset and Integer Carrier Frequency Offset., and . VTC Spring, page 1186-1190. IEEE, (2008)Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 754-758 (2016)Loop and Address Code Optimization for Digital Signal Processors., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (6): 1408-1415 (2002)