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Disambiguation of "Jo, Jihyuck"

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Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 754-758 (2016)

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Jo Baier

Il Jo

Changyeon Jo

Jó Ueyama

Sungho Jo

 

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Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (12): 4196-4207 (2018)Hybrid Convolution Architecture for Energy-Efficient Deep Neural Network Processing., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (5): 2017-2029 (2021)Low-Latency Low-Cost Architecture for Square and Cube Roots., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (9): 1951-1955 (2017)A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory., , , , and . IEEE J. Solid State Circuits, 48 (10): 2531-2540 (2013)Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 754-758 (2016)DREAM: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads., , , , , , and . ASPLOS (4), page 73-86. ACM, (2023)DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks., , , and . IEEE J. Solid State Circuits, 53 (2): 605-618 (2018)Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (7): 1648-1652 (2014)SDRM3: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads., , , , , , and . CoRR, (2022)Area-Efficient Multimode Encoding Architecture for Long BCH Codes., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (12): 872-876 (2013)