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VLSI design of fast fractal image encoder., , and . VDAT, page 1-2. IEEE, (2014)Low-Delay Parallel Architecture for Fractal Image Compression., , and . CSSP, 35 (3): 897-917 (2016)VLSI Friendly Framework for Scalable Video Coding based on Compressed Sensing., , , and . CoRR, (2016)Real-time digitized neural-spike storage scheme in multiple channels for biomedical applications., , and . APSIPA, page 1430-1435. IEEE, (2017)Intelligent Wireless Sensor Nodes for Human Footstep Sound Classification for Security Application., , , , and . CoRR, (2019)Efficient VLSI design of adaptive rood pattern search algorithm for motion estimation of high definition videos., , , , and . Microprocess. Microsystems, (2016)Efficient VLSI design of CAVLC decoder of H.264 for HD videos., , , , and . ISED, page 1-4. IEEE, (2017)Improved single channel phase-aware speech enhancement technique for low signal-to-noise ratio signal., , and . IET Signal Process., 10 (6): 641-650 (2016)An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (4): 1071-1080 (2015)A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (1): 130-140 (2018)