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Low power VLSI architectures for one bit transformation based fast motion estimation., и . IEEE Trans. Consumer Electronics, 56 (4): 2652-2660 (2010)VLSI Friendly Framework for Scalable Video Coding based on Compressed Sensing., , , и . CoRR, (2016)Intelligent Wireless Sensor Nodes for Human Footstep Sound Classification for Security Application., , , , и . CoRR, (2019)Efficient VLSI design of adaptive rood pattern search algorithm for motion estimation of high definition videos., , , , и . Microprocess. Microsystems, (2016)An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis., , и . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (4): 1071-1080 (2015)A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm., , и . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (1): 130-140 (2018)Improved single channel phase-aware speech enhancement technique for low signal-to-noise ratio signal., , и . IET Signal Process., 10 (6): 641-650 (2016)Tensor-Train Long Short-Term Memory for Monaural Speech Enhancement., , и . CoRR, (2018)Embedding delay-based physical unclonable functions in networks-on-chip., , , и . IET Circuits Devices Syst., 15 (1): 27-41 (2021)Efficient VLSI design of CAVLC decoder of H.264 for HD videos., , , , и . ISED, стр. 1-4. IEEE, (2017)