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Disambiguation of "Tejero, Ruben Gran"

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On Fault-Tolerant Microarchitectural Techniques for Voltage Underscaling in On-Chip Memories of CNN Accelerators.

, , , and . DSD, page 138-145. IEEE, (2023)

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Horst Grän

Michael Gran

Fritz Gran

Andreas Gran

Heinz Gran

 

Other publications of authors with the same name

Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems., , , , and . J. Syst. Archit., 59 (9): 667-678 (2013)Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators., , , and . J. Syst. Archit., (2022)A cross-platform OpenVX library for FPGA accelerators., , , , , and . J. Syst. Archit., (2022)A generic framework to integrate data caches in the WCET analysis of real-time systems., , and . J. Syst. Archit., (2021)Adaptive Partitioning for Irregular Applications on Heterogeneous CPU-GPU Chips., , , , , and . ICCS, volume 51 of Procedia Computer Science, page 140-149. Elsevier, (2015)Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches., , , and . IEEE Access, (2020)A Cross-Platform OpenVX Library for FPGA Accelerators., , , , , and . PDP, page 75-83. IEEE, (2021)Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs., , , , , , and . J. Syst. Archit., (2019)An Analytical Model of Memory-Bound Applications Compiled with High Level Synthesis., , , and . FCCM, page 218. IEEE, (2020)An Enhancement for a Scheduling Logic Pipelined over two Cycles ., , , and . ICCD, page 203-209. IEEE, (2006)