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Correction to: Simultaneous multiprocessing in a software-defined heterogeneous FPGA., , , , , , , и . J. Supercomput., 75 (8): 4096-4097 (2019)A fault-tolerant last level cache for CMPs operating at ultra-low voltage., , , , , и . J. Parallel Distributed Comput., (2019)Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage., , , , и . IEEE Trans. Computers, 65 (3): 755-769 (2016)Analysis of network-on-chip topologies for cost-efficient chip multiprocessors., , , , и . Microprocess. Microsystems, (2016)Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems., , , , , , , и . CoRR, (2018)RRCD: Redirección de Registros Basada en Compresión de Datos para Tolerar FallosPermanentes en una GPU., , , и . CoRR, (2021)DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations., , , , , , и . ISCA, стр. 30:1-30:13. ACM, (2023)Abstract Representation of Shared Data for Heterogeneous Computing., , , , , и . LCPC, том 11403 из Lecture Notes in Computer Science, стр. 145-162. Springer, (2017)Dynamic construction of circuits for reactive traffic in homogeneous CMPs., , , , и . DATE, стр. 1-4. European Design and Automation Association, (2014)Analytical Model for Memory-Centric High Level Synthesis-Generated Applications., , , и . IEEE Trans. Computers, 70 (12): 2056-2069 (2021)